Design of Address Generators Using Multiple LUT Cascade on FPGA
نویسندگان
چکیده
This paper presents multiple LUT cascade to realize an address generator that produces unique addresses ranging from 1 to k for k distinct input vectors. We implemented six kinds of address generators using multiple LUT cascades, Xilinx’s CAM (Xilinx IP core), and an address generator using registers and gates on Xilinx Spartan-3 FPGAs. One of our implementations has 76% more throughput, 29.5 times more throughput/slice, and 1.35 times more throughput/memory than Xilinx’s CAM.
منابع مشابه
Implementation of LPM Address Generators on FPGAs
We propose the multiple LUT cascade as a means to configure an ninput LPM (Longest Prefix Match) address generator commonly used in routers to determine the output port given an address. The LPM address generator accepts n-bit addresses which it matches against k stored prefixes. We implement our design on a Xilinx Spartan-3 FPGA for n = 32 and k = 504 ∼ 511. Also, we compare our design to a Xi...
متن کاملA Design Method of Address Generators Using Hash Memories
An address generator produces a unique address from 1 to k when the input that matches one of k registered vectors, and produces 0 for other inputs. This paper presents a method to design an address generator using a hash memory and an LUT cascade. The hash memory realizes about 90% of the registered vectors, while the LUT cascade realizes the remaining 10% of the registered vectors. This metho...
متن کاملAn Efficient LUT Design on FPGA for Memory-Based Multiplication
An efficient Lookup Table (LUT) design for memory-based multiplier is proposed. This multiplier can be preferred in DSP computation where one of the inputs, which is filter coefficient to the multiplier, is fixed. In this design, all possible product terms of input multiplicand with the fixed coefficient are stored directly in memory. In contrast to an earlier proposition Odd Multiple Storage ...
متن کاملProgrammable Logic Device with an 8-stage cascade of 64K-bit Asynchronous SRAMs
The first implementation of a new programmable logic device using LUT(Look-Up Table) cascade architecture is developed in 0.35um CMOS logic process. Eight 64Kb asynchronous SRAMs are simply connected to form an LUT cascade with a few additional circuits. Benchmark results show that it has a competitive performance to FPGAs. 1. Introduction RAMs and PLAs (Programmable Logic Array) are used for p...
متن کاملCompact Numerical Function Generators Based on Quadratic Approximation: Architecture and Synthesis Method
This paper presents an architecture and a synthesis method for compact numerical function generators (NFGs) for trigonometric, logarithmic, square root, reciprocal, and combinations of these functions. Our NFG partitions a given domain of the function into non-uniform segments using an LUT cascade, and approximates the given function by a quadratic polynomial for each segment. Thus, we can impl...
متن کامل